RiscPC
The RiscPC is a RISC OS-based computer originally released by Acorn in 1994. Emphasis was placed on easy expandability, and the ability to run PC software alongside RISC OS software.
Specifications
Revisions
Mk1
Mk2
Mk3
Processors
ARM
The ARM is the microprocessor and the heart of the RiscPC. It comes on a little CPU card which is located on the left side of the machine, directly behind the CD-ROM slot. Every RiscPC has two slots to install a CPU card in each of them; but there is no way to use two of them under RISC OS. One of these slots has to be filled with an ARM CPU-Card since this is the major card that runs the RISC OS Operating System. The second slot does not need to be filled; but its possible to install a compatibility card with an x86 processor here.
The ARM Chips in the Risc PC is of at least Version ARM v3. Such CPUs are capable of using the complete 32 Bit adressrange if they are switched into the so called "32 bit mode" at start. The other variant to use these microprocessors is a so called "26 bit mode". Here the addressrange is 26 bits wide as it has been in the original ARM implementation that has been used in the Archimedes computers. Furthermore its possible to use a mixed mode where programs (executables) are restricted to 26 bit memory addresses but data can use the complete 32 bit addressing. For compatibility and legacy reasons the RISC OS in Risc PCs operates in 26 bit mode. This doesn't affect the wordlength of the registers - registers are 32 bit words ever since on the ARM architechture.
The inclusion of an "wholesome 32 bit" mode into the ARM chips led to a separate register to hold the processor flags - the CPSR (Current Program Status Register).
The memory management is now included directly "on-chip" as an MMU (memory managment unit). This comes together with on-chip cache as standard.
ARM chips of these generations are able to drive an coprocessor, e.g. an FPA (floating point accelerator). BUT: normally this interface has been left out from the chips that are used to build the processor cards (ARM600 with copro interface, ARM610 without). Therefore most, if not all, non-special CPU cards doesn't have the ability to calculate hardware accelerated floating point mathematics.
ARM chips of these generations, and onwards, are switchable (at start) to big-edian or little-endian mode. RISC OS uses big-endianess for its byte order.
ARM610
This is the direct successor to the formerly used ARM 2 and ARM 3 CPU which came in the Archimedes range of computers. ARM610 comes with a unified cache of 4 kByte in size. It runs at 30 MHz. There are variants produced by VLSI (VY86C610) and GEC Plessy Semiconductors (P610ARM/KG/FPNR). ARM610 card needs at least RISC OS 3.5 to run.
ARM710
This is the successor to the 600 (610) line of ARM CPUs. The cache size increased to 8 kByte. It runs on 40 MHz. The minimal RISC OS version that includes support for these CPUs is RISC OS 3.6
ARM810
This has been announced as an upgrade path for the ARM610 CPU cards of the original RiscPCs. When it became available the StrongARM already was in existence - thats why there aren't cards with ARM810 sold to an wider audience; people used the much faster StrongARM instead.
StrongARM
Main page : StrongARM
Kinetic StrongARM
Main page: Kinetic
x86
RISC OS Versions
The RiscPC is compatible with Acorn RISC OS 3.5 through 3.71, RISC OS 4.x, and RISC OS 6.x.
Documents
Links
