GCC processor


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Revision as of 04:11, 23 August 2006

If you wish to improve the code generated by GCC, or know that you will be compiling for a specific machine or range of processors, there are several options that will be of interest when using GCC for RISC OS. What's mentioned here is relevant both to the native released binary and the GCCSDK cross compiler.


Default Target

To be of general use, the distribution GCC defaults to producing code that runs on a broad range of RISC OS machines, GCC produces APCS-32 code that will run on ARM6 or above. That is, code that will work on RiscPC machines or later, and does not make use of any special instructions found on later processors. Binaries and libraries bundled with GCC (in particular, UnixLib) are also compiled in this manner.

What's important to remember here is that for code to be suitable for a given machine, the program and any libaries it is linked with must be compiled for a processor which is compatible with it. GCC can produce ARM2 code, however that sacrificies some performance, and very few RISC OS machines in use today have such a processor. The choice of ARM6 is therefore a balance against performance and machines in use today.

Default Tuning

Tuning is the choice of instructions the compiler chooses to output to minimise load delays and produce the best performing code it can within the choice of instructions for the target that is in use. GCC's default tuning is for XScale - this gives the best all-round performance, especially for XScale and StrongARM targets.

Processor Choices

There is a processor choice that is the best for every single RISC OS machine. However, to avoid explosion of choice, and to focus only on the main groups of machines in use, this is split into 4 main groups.


Although GCC can be instructed to produce code for this (-mapcs26 -mcpu=arm3), the default UnixLib is not compiled for this processor. This requires a custom build of GCCSDK with appropriate options (more details to come)

RiscPC/A7000 class machines

Including ARM6/ARM7/StrongARM RiscPCs, A7000/A7000+, Mico and RiscStation.

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