PC Card Technical Description

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This page describes the hardware of the Acorn Risc PC 486 and 586 cards, as seen from the ARM side. This is entirely based on inference from reading source code and has not been tested for real.

Hardware arrangement

The PC card sits on the Open Bus, the processor bus in the Risc PC, along with the ARM processor. The Open Bus is a relatively simple multiprocessor bus: it is simply the ARM 610 CPU's own bus with the ability for a second processor to take control of the bus and inhibit the ARM. All arbitration and bus sharing is delegated to the second CPU card. The two Open Bus slots are thus equal, and either CPU can plug into either slot. Each CPU card has access to the full memory of the machine, including all peripherals.

To date there have been two products that make use of the Open Bus, the Hydra card (which takes 5 ARM610/ARM710 CPUs and manages multiprocessing between them) and the Aleph One PC Card. The Hydra card was outmoded by the release of the StrongARM processor and so few were made. Some limited support for Hydra exists in NetBSD.

The PC card contains a 486 or 586 processor and the arbitration is provided by a chip called the Gemini ASIC. In addition to arbitration, the Gemini translates the 486-class bus to the ARM format, it presents a means to show system DRAM in a memory map appropriate to the x86, and it allows emulation of ISA-class peripherals by the ARM side. It also (it is believed) implements some of the IBM PC motherboard peripherals (timers, interrupt controllers, DMA etc). There are no peripheral connectors on the PC card, so all I/O is emulated.

There are two versions of the ASIC, Gemini I and Gemini II. It is a descendent of the podule PC cards used on earlier Acorn machines, which were called Elvis.

Mediating between the x86 world and the ARM world is the !PC software (codenamed Diva). This provides RISC OS services such as memory allocation. It provides BIOS and Windows drivers that use the ARM to accelerate disc, network, video and sound operations and translate these into the RISC OS world. It also provides a GUI to interact with and configure the PC system.

Gemini ASIC memory map

The Gemini ASIC contains the following registers. Since the OpenBus does not have an address allocation for the CPU cards, they are fitted into a spare space in the physical memory map.

0x03700000 MBCR Memory block control registers (8x consecutive 32 bit words)
0x03710000 MMCR Memory map control register
0x03720000 IOMCR I/O map control register (controls if devices are ISA-based or ARM mailboxes)
0x03730000 MASR Mailbox address/status register
0x03730004 MDR Mailbox data register
0x03740000 PICR Processor / Interrupt Control Register
0x03750000 MISCR Miscellaneous control reg (read/write)
0x03760000 CFGR Configuration register (RAM/cache sizes)
0x03770000 XREG External register
0x03780000 GPIO General purpose IO (4x consecutive 32 bit words)
0x03790000 FDDATA Floppy disk data reg, Read/Write
0x03790004 FDCTRL Floppy disk ctrl/status register, write
0x03790004 FDSTAT Floppy disk ctrl/status register, read
0x037A0000 REV2R Revision 2 register (Gemini II ASIC only)
0x037F0000 TESTR Test register

Further details on these registers can be gleaned from header file PC.CPU.h.Gemini in the Src306.zip source code archive.

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