[Rpcemu] RPCEmu Spoon Edition 0.8.3
rpcemu-list at howkins.me.uk
Thu Apr 23 11:05:32 PDT 2009
My intention was to send this reply to the mailing list, but I
mistakenly sent it directly to Tom, so I am forwarding it now.
---------- Forwarded message ----------
From: Matthew Howkins <rpcemu-list at howkins.me.uk>
Subject: Re: [Rpcemu] RPCEmu Spoon Edition 0.8.3
To: Tom Walker <tommowalker at yahoo.co.uk>
> Might I ask which bugs have been fixed? The main ARM emulation is used in another emulator (two if you include Arculator as well, though that's technically an older branch) so it would be helpful to know.
> I know one of the aborts (can't remember which one) was broken, fixing that makes ROS 6 abort instead of just hanging.
In no particular order:
- The masks used to identify multiply and long multiply instructions
were corrected. The tests now look like:
if ((opcode & 0xf0) == 0x90) ...
- The decoding of SWPB was changed, because when the instructions are
decoded using ((opcode >> 20) & 0xff), the code was placed in the
wrong case statement. It should be at 0x14, not 0x12. To fix this for
ArmDynarec.c and ArmDynarecOps.h I renamed a couple of functions to
reflect this change.
- I reinstated a patch that was originally written by John-Mark Bell,
but seemed to have got lost. This was a fix for the instruction MSR
CPSR,reg which updates the flags if requested.
- The calls to the exception handler for Prefetch and Data Aborts had
the wrong offsets (when the pipelining and offset for R15 is taken
into account). I presume this is what you are referring to above.
It is difficult to measure the impact of these errors, but I do know
that the last two changes were particularly significant in enabling
the successful boot of Pace RISC OS 4 (Ursula) and RISC OS 6 Preview
3. Prior to these changes both would just hang early on in the boot
I am happy to provide the above changes in 'patch' format if it will
help you review and integrate them into other code.
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