32-bit Changes

Alex Waugh alex at alexwaugh.com
Mon Apr 21 11:52:58 PDT 2003


A few comments about the 32bit changes:

> Index: unixlib/source/signal/_signal.s
> ===================================================================
> RCS file: /usr/local/cvsroot/gccsdk/unixlib/source/signal/_signal.s,v
> retrieving revision 1.7
> retrieving revision 1.8
> diff -u -r1.7 -r1.8
> --- unixlib/source/signal/_signal.s	15 Dec 2002 13:16:55 -0000	1.7
> +++ unixlib/source/signal/_signal.s	21 Apr 2003 10:48:45 -0000	1.8
> @@ -307,10 +309,17 @@
>  	; Entered in USR mode. Setup an APCS stack frame
>  	; so we can get a proper stack backtrace in case anything
>  	; goes horribly wrong.
> +
> +	STMFD	sp!, {a1-pc} ; Don't really want to store sp modified
> +

What is the purpose of this STM? There doesn't seem to be a matching
LDM so if the error handler returned then things would break (although
I'm not sure if it is sensible for the error handler to return anyway).
I assume you know that the stored value of sp is UNPREDICTABLE, is this
what the comment is refering to?

>  	MOV	ip, sp
>  	STMFD	sp!, {a1, a2, a3, a4, fp, ip, lr, pc}
> +
>  	SUB	fp, ip, #4
>  
> +	LDR	a1, =|__ul_errfp|     ; Save error FP backtrace
> +	STR	fp, [a1]
> +
>  	[ __FEATURE_PTHREADS = 1
>  	LDR	a1, =|__pthread_system_running|
>  	LDR	a1, [a1]
> @@ -533,9 +557,9 @@
>  	BL	|__pthread_disable_ints|
>  	]
>  
> -	TEQP	pc, #IFlag	; USR mode IntOff (irq off, fiq on)
> +        MSR	CPSR_c, #IFlag32 ; USR mode IntOff (irq off, fiq on)

I feel as if I'm missing something, but wouldn't this change into USR32
mode, which is fine on RISC OS 5 but on earlier machines you'd want to
change to USR26. I'd expect things to break horribly if this was the
case though.

>  	; The USR mode registers r0-r15 are extracted from the callback
> -	; register block while irqs are disabled. The registers are then
> +	; register block while IRQs are disabled. The registers are then
>  	; saved on the USR mode stack while ensuring that the USR sp is
>  	; valid by not pointing above saved data. So, load the registers,
>  	; allocate room on the stack and then store the original USR
> @@ -586,11 +614,13 @@
>  	]
>  
>  	ADD	sp,v1,#16		; skip signal frame
> -	LDMFD	sp,{a1,a2,a3,a4,v1,v2,v3,v4,v5,v6,sl,fp,ip,sp,lr,pc}^
> +	LDMFD	sp,{a1,a2,a3,a4,v1,v2,v3,v4,v5,v6,sl,fp,ip,sp,lr,pc}
>  
>  	; User registers are preserved in here for the callback execution.
>  	EXPORT	|__cbreg|
> -|__cbreg|	%	64
> +|__cbreg|	%	4 * 17; R0-R15 and CPSR in 32-bit mode

The saved CPSR isn't being restored anywhere, AFAICT.
I've been making a few pthreads related changes to the callback handler
and how it restores registers, so I'll fix this one if you like.

> +        EXPORT  |abortpc|
> +|abortpc|       %       12
>  
>  	; bit 0 Escape condition flag
>  	; bit 1 no re-execute inst. flag
> @@ -604,15 +634,18 @@
>  
>  ; Exit handler
>  ; Called in USR mode
> -	IMPORT	|_exit|
> +	IMPORT	|exit|
>  	EXPORT	|__h_exit|
>  	NAME	__h_exit
>  |__h_exit|
> -	ORR	lr,pc,#&0c000000	; USR mode IntOff
> -	MOVS	pc,lr
> +	TEQ	r0,r0			; Set Z
> +	TEQ	pc,pc			; EQ if 32-bit mode
> +	MSREQ	CPSR_c, #&50		; USR mode IntOff

That is disabling FIQs, not IRQs.

Alex

-- 
Alex Waugh                                           alex at alexwaugh.com

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